As the size of semiconductor devices continues to decrease, the ability to create standard cell library logic devices, such as scan-D flip-flops and multiplexers, becomes more difficult. This is particularly the case at the 20 nm node, where lithographic limitation results in a lack of scaling of standard cell library devices.
Referring to FIG. 1, typical semiconductor devices 100 include a plurality of transistors 102 formed within a diffusion region 104. The semiconductor devices 100 utilize power rails 106, as part of a first metal layer 107, to deliver a reference voltage and/or ground to the transistors 102. Specifically, the power rail 106 includes power tabs 108 that extend into the diffusion region 104. A via 110 then electrically connects the power tab 108 to a source (not shown) or a drain (not shown) of one of the transistors 102.
The projection of the power tabs 108 into the diffusion region 104 causes difficulties, as the metal layer 107 is also routinely utilized for local interconnection between the transistors 102 and as cell pins 112. This leads to a very complicated patterning for the first metal layer 107, as is shown in FIG. 2, which routinely leads to fabrication difficulties and/or compromises in standard cell design. One solution is to use a second metal layer (not shown) on a different plane from the first metal layer 107. However, the use of the second metal layer reduces routing efficiency and results in a larger and more expensive implementation of the semiconductor device 100.
Accordingly, it is desirable to provide a semiconductor device arrangement with less resource conflict in the metal layer. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.